Why socdvtech

VLSI Internship Overview

  • Training is divided into 2 aspects:
    • Learning Phase (3 Months)
    • Application Phase (9 Months)
  • Learning Phase: Intern will undergo 3 months of exhaustive training on Advanced Digital Design, Verilog, SystemVerilog and UVM basics along with some standard protocols like AXI, AHB, Ethernet MAC, etc. Intern will also get a practical exposure to various EDA tools while working on above protocols using SV & UVM.
  • Application Phase: Intern will be working on industry standard projects with trainer guidance. Same projects can be used as an MTech/BTech Projects.