Design Implementation

SOCDV Technologies has Design Implementation expertize in following technology nodes:
• TSMC 20nm CMOS Logic 1P10M Process
• TSMC 28nm HP & HPM
• TSMC 40nm, 45nm, and 60nm
Design Implementation Expertize:
• RTL integration, Synthesis, DTF, ATPG and Formal Equivalence checks
• Backend Implementation
o Floor Planning
• STA and Design Analysis
o Constraints Generation
o Timing Signoff
o Xtalk, Noise: Signal Integrity
• Physical Verification and DSM Issues
o LVS, DRC, ERC, ESD, Antenna
o OPC, CMP, Yield
Tool Expertize:
• Design Compiler, RTL Compiler, Conformal LEC, Spyglass
• ICC, SOC Encounter, Olympus, Talus
• PT, EPS and EDI
• Calibre, Hercules, Redhawk
Library & Flow Development:
• Testchip
o TSMC 20nm CMOS Logic 1P10M Process
o TSMC 28nm HP & HPM
o TSMC 40nm, 45nm, and 60nm
• Standard Cell, Memory and IO Library modeling
o Circuit design
o Characterization & view generation
• Testchip
o Semi custom and full custom testchip for IP/Memory Silicon qualification
• Flow & Methodology
o Tool integration
o Automation using Perl, TCL, Skill