Whatever your career prospects may be SOCDV Tech offers the opportunity to work with most advanced technologies along with some of the highly innovative & talented minds in the industry.

Presently we have requirements for following positions :

  1. ASIC/SoC Design Engineer
  2. Experience: 3 - 8 Yrs
    Qualification: Bachelors or Masters (Computer/Electronics Engineering)
    Location: Bangalore
    Job Description:

    • Expertise in understanding, gathering and finalizing the requirements from the front end design perspective.
    • Translate the requirements and architecture into micro-architecture/detailed design
    • Capable of bus fabric implementation for SOCs and full chip integration
    • Competent in basic digital design concepts, Boolean arithmetic, decoding, interfacing, clocking, setup-hold timing concepts, multi-clock design
    • Hands on experience in Verilog/VHDL/System Verilog for design.
    • Hands on experience in NCSIM/Modelsim/VCS/QuestaSim.
    • Good understanding of basic concepts of simulation verification, code and functional coverage
    • Aware of verification/DFT/PD friendly full chip implementation
    • Debugging the RTL code and gate level netlists in simulation environment and in board level environment
    • Hands on experience in Linting, Synthesis, Static Timing Analysis and LEC
    • Knowledge of AHB, AXI bus interfaces and protocol

2. ASIC/SoC Verification Lead
Experience: 3 – 8 Yrs
Qualification: Bachelors or Masters (Computer/Electronics Engineering)
Location: Bangalore
Job Description:
As a part of the verification team, ASIC/SoC Verification engineers are responsible for implementing the verification models, integrating the verification environments, develop script based utilities and support verification activities.
The key functions and responsibilities are the following:
• Develop block and system-level test benches and verification environments using Verilog/SystemVerilog, C/C++, SystemC, VMM/OVM/UVM and/or other verification languages as appropriate.
• Develop support utilities for verification automation, test bench automation, regression and other verification enhancements to improve productivity and functional coverage.
• Work with design and verification teams and provide technical support for verification activities.
• Support the development of verification test plans, test suites and verification activities
Essential Technical Expertise:
• Experience in ASIC/SoC verification activities and should have participated in successful completion of at least one ASIC/SoC project from Specifications to Silicon.
• Must have good understanding of embedded processor based SoC architecture and must have completed verification of one or moreembedded processor based SoC. Good understanding of ARM processor architecture is plus.
• Must be knowledgeable on ASIC verification methodologies and levels functional, RTL, gate level, Low power and processor verification.
• Must have experience in developing BFM and functional models in Verilog/System Verilog/ OVM/VMM/UVM.
• Proven experience of the design verification methodologies such as VMM/OVM/UVM, assertion based coverage driven verification (code & functional coverage), constraint random test generation.
• Must have experience in Make and proficient in scripting using perl, Tcl,etc.
• Must have worked on developing verification environment and test cases.
• Must have conducted functional simulations, exposure to functional coverage and bug management schemes.
• Protocol Knowledge on PCIe, USB2.0/3.0, Ethernet and LPDDR2/DDR3 is added advantage.
• Self-motivation, flexibility, with strong inter-personal skills.
• Good communication skills, oral and written.
3. Physical Design Lead
Experience: 3 – 8 Yrs
Qualification: Bachelors or Masters (Computer/Electronics Engineering)
Location: Bangalore
Job Description:
Hands on experience with Implementation (PnR& Signoff) of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm)
• Lead all aspects of SoC Physical Design with strong expertise in the area of chip/partition floor-planning, design partition creation, budgeting and feedthrough planning
• Work alongside RTL/Synthesis/DFT teams to define design partitions and create floorplan as per the design data flow
• Work closely with library, technology and Analog IP teams for physical design requirements
• Work closely with CAD teams and involve in methodology development and improvement
• Own SoC/partition physical design activities while managing a team of 4-5 engineers
• Should have handled Netlist to GDS II implementation at Chip/partition level for atleast 2-3 designs
• Hands-on expertise with technology nodes like 28nm, 16nm and below
• Good knowledge of EDA tools from Synopsys, Cadence and Mentor, particularly with ICCII & Calibre
• Excellent understanding of design partitioning & budgeting along with hands-on experience in Chip/partition floor planning, placement optimizations, Clock planning and routing.
• Good understanding of low power implementation techniques and static low power checks
• IO ring design and bump planning is a plus
• Being proficient in TCL, Perl scripting is a plus
4. Embedded SW Developer
Experience: 2 – 5 Yrs
Qualification: Bachelors or Masters (Computer/Electronics Engineering)
Location: Bangalore
Job Description:
Mandatory skills:
• Proficiency in C programming & Data structures’ concepts & implementation.
• Good understanding of Linux internals- memory management, process management, multi-threading.
• Knowledge on SW debugging & use of JTAG debuggers.
• Understanding of device drivers for SPI, UART, I2C, USB etc.
• Effective communication/presentation skills.
Desired skills:
• ARM architecture & assembly instructions’ knowledge.
• Hands on with Perl/Python/shell scripting.
• Understanding of Android architecture.
5. ASIC Verification Engineer
Experience : 2 - 5 Yrs
Qualification : BE / BTech or ME / MTech / MS in EE / ECE / Electrical
Location : Bangalore
Job Description:
• Working experience in IP / SoC verification
• Experience to develop block level / system level verification environments using System Verilog and UVM / OVM
• Experience to develop BFMs / Checkers / monitors / Scoreboard.
• Should have the capability to debug test failures to find the root cause.
• Should have worked on code / functional coverage.
• Experience in constrained random testing is a plus.
• Strong knowledge on one or more protocol - PCIe / DDR / Ethernet / USB / ARM / Bluetooth
• Knowledge of scripting languages like Perl, Tcl